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Hardware Standards

The rules every OpenSkyhawk board follows. These aren't preferences — they're the constraints that keep boards buildable, inspectable, and interchangeable across the cockpit. This page is the hub; the detail lives on the pages it links.

Component packages — must be inspectable

Every package must be visually inspectable after reflow. A T962 reflow oven handles the soldering; the limit is inspection, not soldering. So bottom-terminated parts are out.

Acceptable Not acceptable
SOIC, SSOP, TSSOP, HTSSOP QFN, DFN, WSON
LQFP BGA, LGA
SOT-23, SOT-223 any fully bottom-terminated package
Through-hole

HTSSOP is fine — its side leads are the critical joints; the exposed thermal pad is verified by continuity check.

MCU

  • CAN nodes: STM32F103 (LQFP48). All boards default to the STM32F103C8 (64 KB) — both PanelGroup nodes and PanelBridge (which carries the DCS-BIOS input map but still compiles to ~26 KB flash). The STM32F103CB (128 KB) is a drop-in fallback on the same footprint, needed by no board currently.
  • Requires an external 8 MHz crystal — the internal RC oscillator isn't accurate enough for 500 kbps CAN.
  • PA11/PA12 are shared between USB and CAN; pick one at init (CAN, in production).
  • HID controls: RP2040 off-the-shelf modules (flight stick, throttle, pedals, button boxes). No custom PCB.

Power

A PC ATX supply distributes 12 V and 5 V on the main bus; each board makes its own 3.3 V locally with an AMS1117-3.3. Local decoupling (100 nF + 10 µF per rail) is required on every board. Full detail — rails, budgets, the switching buck for high-current boards — is on the Power Architecture page.

CAN transceiver

SN65HVD230 (SOIC-8, 3.3 V), one per STM32 board, on PA11 (RX) / PA12 (TX). 120 Ω termination across CANH/CANL at the two end nodes only. See CAN Bus Protocol for the protocol side.

LED backlighting

Confirmed by bench testing: 5-LED series strings, MOSFET-switched per zone, one current-limiting resistor per string.

  • 5 × 5050 red LEDs in series per string (~10 V at 12 V supply, ~2 V resistor headroom)
  • One resistor per string — 120 Ω default (≈18 mA); 100 Ω for bright panels, 180 Ω for dim/night zones. (47 Ω was rejected — the resistor overheated.)
  • One AO3400A N-channel MOSFET per zone (SOT-23, 30 V — needed for margin over the 19.9 V SMBJ12A clamp on the 12 V rail; IRLML2502's 20 V sits too close), low-side, gate driven directly by STM32 3.3 V PWM (no gate driver). PWM duty sets average brightness.
  • LEDs on the front face; resistors, MOSFETs, and everything else on the back.

Shift-register I/O — 74HC165 / 74HC595 (ShiftBus)

The SPI shift-register backend for sub-panel I/O, bench-decided against the MCP23017 (see D9). Panels are I²C-class or SPI-class by their connector, chosen by physics: rotary encoders or fast gauges (≳150 °/s) → SPI-class; everything else is fine on I²C-class. Key rules:

  • 74HC165 inputs: bussed 10 k resistor array to 3V3 on all 8 inputs of every chip, used or not; switch/encoder commons to GND (active-low).
  • 74HC595 outputs: indicator LEDs ≤4 mA drive directly with a series resistor; anything above ~6 mA, any 5 V/12 V rail load, or a chip total nearing 70 mA gets a 2N7002 MOSFET.
  • DRV8833 motor supply is 5 V — never the 12 V rail (10.8 V absolute maximum). Servos take 12 V through a panel-local buck, never a 5 V rail.
  • The SPI bus is dedicated — a '165's data output never tristates, so the bus is the shift chains' alone. Chains daisy without limit; capacity never needs a second bus.
  • Standard pins: SCK=PB3 · MISO=PB4 · MOSI=PB5 · LOAD=PB8 · LATCH=PB9 — one contiguous header run with I²C1. I²C interrupt pins are assigned around it; see the reference below.

Full rules, the measured numbers, and chip-placement guidance: docs/_source/hardware-standards.md (Shift-Register I/O section). Harness pinouts: the Connector & Harness Guide.

Silkscreen

Checked on every board before gerber export — a silk error is only found after fab. Key rules:

  • Every power and bus connector pin is labelled with its signal — 12V, 5V, CANH, CANL, GND beside each pad of the Mini-Fit Jr bus connectors. A reversed harness destroys the board, so here silk is a safety feature. Off-board headers (I²C, ShiftBus, SWD) get the same treatment.
  • Label the signal, not the net — a pin behind a series resistor is SDA, not its auto-generated Net-(J2-Pin_1) name.
  • Legends are free silk text, never a footprint Value override — an override breaks schematic parity and is silently deleted by the next Update PCB from Schematic.
  • Revision line on the back silk: REVISION 0.2.0 | BOARD NAME, bumped in the same change as the board revision. Identify a board revision as 0.2.0 everywhere — "Rev 2" names a round of work, never the hardware.

Full rules, the text format, and the four-point pre-gerber gate: docs/_source/hardware-standards.md (Silkscreen).

Releases

Hardware releases work like firmware's: commits under PCB/ keep a draft release hardware X.Y.Z pull request up to date, and merging it is the release (hardware-vX.Y.Z). A release means the boards in it are ready — built, brought up, and verified — and which boards those are is listed in PCB/manifest.yaml. The release notes list each board and what changed in it. Every board folder's README.md says whether it is Released, In progress, or Deprecated. The model is design decision D10; the standard and release checklist are in docs/_source/hardware-standards.md (Releases).

The other reference pages

MCP23017 GPA7 / GPB7 — output only

A confirmed silicon bug means GPA7 and GPB7 must never be configured as inputs — the SDA signal can be corrupted if the pin voltage changes mid-transmission. That leaves 14 input pins per chip (GPA0–GPA6, GPB0–GPB6). GPA7/GPB7 may drive LEDs or other outputs freely.